1/7 greenfield V600AT february 2005 this is preliminary information on a new product now in development. details are subject to change without notice. 1 product features system-on-chip integrating an arm926 micro- controller, embedded fpga and embedded dram 16 mbit of embedded sdram arm926: 32/16-bit risc architecture with instruction set for maximum performance, flexibility and high code density running at 300 mhz, and with amba bus architecture operating at ? cpu frequency. built-in memory management unit for os support 32 kbytes l1 program cache and 16kbytes l1 data cache embedded fpga array: 150kgates asic equivalent running at 200mhz power-on reset module with power supply voltage monitoring two 10-bit 8-channel analog-to-digital converters with sampling rate of 1 msps four 10-bit single channel analog-to-digital converters with sampling rate of 1 msps three 10-bit digital-to-analog converters with sampling rate of 1 msps external memory controller with ddr sdram support five i 2 c bus interfaces synchronous serial port, including spi and microware compatible dual single-channel hdlc controllers 16-bit general purpose i/o 32-bit timers uart 32-channel dma engines vectored interrupt controller system controller, pll and power on reset ethernet mac two hdlc multi-channel serial port watchdog on-chip emulation / real-time embedded trace development tools available 2 overview/description the greenfield system-on-chip is a low-cost, versatile high performance and reconfigurable mi- cro-controller able to manage control tasks within complex telecommunication infrastructure equip- ment such as base transceiver stations. the greenfield assp is designed to be ex- tremely flexible and it can be used in many places within telecom equipment. it can fulfill control tasks as well as monitoring. figure 1 shows a block diagram of the greenfield. the embedded fpga technology offers a high de- gree of flexibility. it allows the greenfield to be reconfigured. the embedded fpga can be used to remap i/os or to implement specific custom logic. data brief reconfigurable micro-controller rev. 3 fi gure 1. p ac k age table 1. order codes part numbers package V600AT pbga/hsp-561 V600ATr pbga/hsp-561 in tape & reel pbga/hsp-561
greenfield - V600AT 2/7 figure 2. greenfield block diagram 3 architecture overview the greenfield micro-controller includes an arm926 micro-controller, used as a master for the com- plete system. it allows the setup of peripherals within the system, as well as the control of the data flow. the greenfield used with external flash devices can boot in stand-alone mode. the embedded fpga can be setup using an external serial flash, with the help of an i 2 c or spi bus interface. the dma controller, allows data exchanges between specific parts of the system such as the high speed communication peripherals, or the adc/dac converters. the greenfield bus architecture is based on the multi-layer ahb. this bus architecture provides a large amount of bandwidth in the system, and prevents the bus architecture from being a bottleneck. an 16mbit memory provides data storage capability shared among the cpu, and i/o peripherals. it allows storage of a collection of data coming from hdlc controllers, ethernet or other dma-based peripherals. the embedded fpga offers 150k gates of reconfigurable logic, which can represent simple custom in- terfaces, as well, as more complex logic designs. the fpga array is connected to the rest of the system, through built-in ahb interfaces. it is connected to specific system parts such as interrupt controller, timer, clock generation, system controller, etc? dpram memories are available around the fpga macro, to allow processing storage or data exchange between the embedded fpga prototyped logic and the rest of the system. 4 arm926 overview the greenfield is based on the open arm primexsys platform built around the arm926 core and includes a set of peripherals and an amba multi-layer ahb system bus for maximized throughput. the arm sub system contains a set of standard peripherals including timers, watchdog, 32-bit gpios, and clock/system controller. beside the standard peripherals the arm sub system also contains a set of high-speed dma peripherals including serdes interface, hdlc controller, and ethernet mac. a two master ports dma engine manages all dma operations over the system. an interrupt controller with 32 standard interrupts and 16-vectored interrupts provides a simple software interface to the interrupt system. for expansion purpose, one external memory controller can address sram, flash, rom or i/o devices. etm9 vectored interrupt controller multi port memory controller 2xuart 5 x i 2 c 6x32-bit timers 16-bit gpio watch dog ethernet mac debug por 16 mbit embedded dram 3x 10-bit dac system controller 4x hdlc dma 1 m s m dma 2 m s m static memory controller msp 6x 10-bit adc rtc ethernet mac 926 transfer cross bar ahb2mem 2 kb x 16 dpram 2 kb x 8 dpram 2 kb x 16 dpram 2 kb x 8 dpram 2 kb x 8 dpram 2 kb x 8 dpram reconfigurable interface (150 kgates) 1 00 dma dma ahb - apb
3/7 greenfield - V600AT 5 embedded fpga overview the greenfield includes an embedded fpga array, composed of 7168 logic elements over 56 clus- ters. 1 cluster includes 128 logic elements. overall, the array is equivalent to 150k asic gates. the macro architecture is a multi-stage hierarchical interconnect network ensuring a predictable and bounded delay between any programmable element and/or i/os. a logic element is composed of 4 inputs and 1 output sram programmable element, including a 4 input lut and a general-purpose storage element. figure 3. embedded fpga macro architecture 6 adc-dac overview the greenfield includes two 8-input 10-bit analog-to-digital converters, with sampling rates of 1 msps. the adcs have an input range of 0 to 2.4 v. it includes also, four 10-bit digital-to-analog converte r, delivering 1 msps with an output range from 0 to 2v. both adc and dac implement low-power modes with fast wake-up times. 7 development support stmicroelectronics provides a complete set of development tools around the greenfield micro-control- ler, to evaluate performance, develop, debug and integrate application code. 7.1 fpga development tools: to design and program the embedded fpga array, a comprehensive and standard development flow al- lows the use of 3rd party tools for synthesis. the mapping on the embedded fpga array is performed by dedicated proprietary tools which take advantage of the fpga technology to obtain optimal results. global routing network cluster logic element local routing network logic element cluster logic element local routing network logic element i i i i o o o o programming & test
greenfield - V600AT 4/7 figure 4. embedded fpga design flow 7.2 software development tools: software development tools for the arm926 include an integrated development environment tool, the c/c++ compiler, assembler and linker, instruction set simulator and os-aware debugger for simulation and emulation debug. beside standard software development tools, rtos dedicated tools for applica- tion-level debugging and analysis of embedded applications are also available. they include runtime de- bugging, system and process information viewing, manual process control, system event tracing and monitoring, memory analysis and message search, cpu usage analysis and more. 7.3 hardware development tools in addition to the software development tools, a complete set of hardware tools help greenfield users to speed-up the development of new applications. the greenfield starter kit can be used to evaluate greenfield performance, as well as to develop software applications. the starter kit offers a basic set of peripherals in addition to the greenfield built-in peripherals. the starter kit is usable as a stand-alone board, or as a daughter card. in the latter case, multiple daughter cards can be plugged on a system ap- plication backbone (mother board), which represents the prototype system. the greenfield starter kit includes a complete board support package. front end logic blocs netlist compiler configuration files simulation model generator static timing analyzer binary generator programming bit stream translation libraries rtl gate libraries operators synthesis edif verilog design verification greenfield simulation model static timing analysis report
5/7 greenfield - V600AT 8 package information figure 5. pbga/hsp-561 (27x27x2.36mm) mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.36 0.093 a1 0.30 0.012 a2 1.73 0.068 b 0.50 0.60 0.70 0.020 0.024 0.027 d 26.80 27.00 27.20 1.055 1.071 1.070 d1 25.00 0.984 d2 24.00 0.945 e 26.80 27.00 27.20 1.055 1.071 1.070 e1 25.00 0.984 e2 24.00 0.945 e1.00 0.039 f1.00 0.039 h 19.50 0.768 ddd 0.20 0.008 eee 0.25 0.010 fff 0.10 0.004 pbga/hsp-561 (27x27x2.36mm) heat spreader plastic ball grid array 7633273 a seating plane bottom view c c a f d d1 a1 a2 d2 e2 e1 e f h ddd (1) - the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug - a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. - exact shape of each corner is optional. e a b
greenfield - V600AT 6/7 9 revision history table 2. revision history date revision description of changes january 2005 1 first issue february 2005 2 slightly modified feature section on page 1. 14th february 2005 3 modified feature on page 1 and changed the block diagram on page 2.
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